Field of the Invention
The present invention relates generally to a semiconductor device, and more specifically, to a highly integrated structure of an NAND type mask ROM (Read Only Memory).
The present invention further relates to a method of manufacturing an NAND type mask ROM having such a highly integrated structure.
FIG. 17 is a diagram showing an equivalent circuit of the memory cell array of a conventional NAND type mask ROM utilizing an n channel type transistor, and FIG. 11 is a top plan view showing the structure of the memory cell array corresponding to FIG. 17. Referring to these figures, on the main surface of a silicon substrate, a first MOS transistor train (a train) and a second MOS transistor train (b train) both formed of a plurality of MOS transistors connected in series are formed parallel to each other extending in the direction of columns. These two transistor trains (a train, b train) are insulated and isolated from each other by an LOCOS (Local Oxidation of Silicon) isolation film 4. The gate electrodes (3S0, 3S1) and word lines (30-37) of MOS transistors are formed extending parallel to each other in the direction of rows on the main surface of the silicon substrate.
FIG. 12 illustrates a sectional structure taken along line X--X in FIG. 11. The plurality of MOS transistors formed on the main surface of a silicon substrate 6 are connected in series sharing impurity regions with each other. The MOS transistor train of a plurality of MOS transistors includes a transistor of enhancement type and a transistor of depletion type. In the case of the depletion type transistor, an arbitrary transistor is formed into depletion type depending upon data to be stored therein. More specifically, in the NAND type mask ROM, ROM data "1"/"0" is stored as the "presence/absence" of depletion implantation to the MOS transistor.
The operation of a conventional NAND type mask ROM will be described in conjunction with FIGS. 17, 11 and 12.
In FIG. 17, transistors having their channel regions depicted by oblique lines (for example 5S0a, 5S1b, 51a . . . ) are depletion type transistors, and the other transistors are of enhancement type. Gate electrodes 3S0 and 3S1 are select gates for selecting the a train or b train of MOS transistors.
In operation, when data is read out from a bit line 53a of WL3-a train, select gate 3S0 is turned off, 3S1 is turned on, word line WL3 (33) of the read bit is turned off, and the other word lines WL0-WL2, and WL4-WL7 are turned on. In this state, current does not flow through b train side, because transistor 5S0b is in the state of off. With the non-selected word lines (WL0-WL2, WL4-WL7) being all supplied with ON state current, current can flow through the bits (50a-52a, 54a-57a) corresponding to these non-selected wordlines regardless of the bits being enhancement type or depletion type. Whether or not current flows through the a train is determined depending upon whether or not current can flow the bit 53a corresponding to word line WL3 selected in this state. Suppose that the selected read bit 53a is a depletion type transistor. Therefore, if current flows through read bit 53a, current flows through the a train side, and then the current flows through bit line 2. The data of read bit 53a is determined to be "1" by sensing the current through bit line 2.
Conversely, when select gate 3S0 is turned on, 3S1 is turned off and word line WL3 is selected, the current path is cut off because read bit 53b is formed of an enhancement type transistor. Current therefore does not flow through the b train, and the data of read bit 53b is determined to be "0".
A description will be provided on the structure of an MOS transistor constituting each of the bits. FIG. 13 is a sectional view showing the structure of series-connected MOS transistors. MOS transistor trains constituting bits include a depletion type MOS transistor 10a and an enhancement type MOS transistor 10b. The transistors both have the same basic structure. In other words, the transistors both include a pair of N.sup.+ sources/drains 13, 13, a gate insulating layer 12 and a gate electrode 11. Depletion type MOS transistor 10a has a depletion implantation layer 14 at least in its channel region. Depletion implantation layer 14 permits current to flow through the source-drain region even when no voltage is applied to the gate electrode. More specifically, its threshold voltage is negative. Conversely, in the case of enhancement type MOS transistor 10b, drain current starts flowing through the source-drain regions 13, 13 with gate electrode 11 being supplied with a positive gate voltage.
A description will be provided on a method of manufacturing the series-connected MOS transistor train shown in FIG. 13. FIGS. 14-16 are sectional views showing the structure of the MOS transistor train shown in FIG. 13 for illustrating the manufacturing steps in their order.
As shown in FIG. 14, an LOCOS isolation film (not shown) is formed at a prescribed position on the main surface of silicon substrate 6 by means of LOCOS method. Then, impurity ions 26 are implanted into the surface of silicon substrate 6 for adjusting the threshold of the transistor.
As shown in FIG. 15, a mask layer 27 is formed at a prescribed position in a transistor formation region on the silicon substrate. Using mask layer 27, impurity ions 28 such as phosphorus or arsenic (in the case of n channel type) are implanted into the region of silicon substrate 6 in which a depletion type transistor is to be formed. Depletion implantation layer 14 is thus formed.
As shown in FIG. 16, after removal of mask layer 27, a gate insulating layer 12 is formed on the surface of silicon substrate 6, by, for example, heat-oxidation method. Further formed on the surface of gate insulating layer 12 is conductive layer formed of such as polycrystalline silicon, or a two-layered film of high-melting point metal silicide and polycrystalline silicon, which is patterned into a prescribed form. A plurality of gate electrodes are thus formed. Then, using the gate electrodes as masks, n type impurity ions 29 are implanted, thereby forming the source/drain 13 of the MOS transistor. A series-connected structure of enhancement type and depletion type MOS transistors is formed by the foregoing steps.
Subsequently, interlayer insulating layers, bit lines and source lines are formed.
In the field of semiconductor devices, a demand for increasing integration density is inevitable in order to expand storage capacities. The structures of devices constituting a memory should be shrunk for higher integration density. In the case of the memory cell array of a conventional NAND type mask ROM as described above, the size of the series-connected MOS transistor structure should be reduced for the purpose of reducing the size of the entire structure. The reducing the size of a MOS transistor is however encountered with the following problem.
(1) Referring to FIG. 13, in the case of an enhancement type transistor, as for the gate length of gate electrode 11, a length enough for maintaining the breakdown voltage of the source-drain region is necessary which can cut off current flowing through the source-drain region. More specifically, it is necessary to secure such a distance between the source and drain that punch through phenomenon can be restrained from taking place in the source-drain region.
(2) The spacing of gate electrodes 11, 11 of adjacent MOS transistors is limited by resolution given by an exposure device or performance by an etching device in the process of patterning.
According to the above-stated limitations, the gate length is about 0.8 .mu.m and the spacing of gate electrodes 11, 11 is about 0.8 .mu.m in the memory cell array of the conventional mask ROM shown in FIG. 13.
As described above, in a conventional mask ROM having a memory cell array in which MOS transistors are disposed in series on the main surface of a silicon substrate, the limitations given by MOS transistor characteristics as well as manufacture stand in the way of achieving further reduction of the size.